Semiconductive wafers are used as substrates for the formation of microprocessor, DRAM, logic, and memory circuits. Such semiconductive wafers can comprise, for example, silicon. Ideally, the semiconductive wafers will comprise a single crystal of semiconductive material. For instance, silicon wafers are generally taken from crystals grown by a Czochralski (CZ) method or a float zone (FZ) method. The CZ method comprises growing a crystalline ingot by dipping a seed crystal into a silicon melt and then slowly extracting the seed. Liquid from the silicon melt crystallizes on the seed as it is extracted. Preferably, oxygen and other impurities will be excluded as the silicon melt is crystallized. Otherwise, the impurities can become incorporated into the silicon crystal during growth and cause defects in the crystalline lattice. For instance, if oxygen is introduced during cooling of a silicon melt, an oxygen-induced stacking fault (OSF) will typically result. Such OSF can adversely affect circuit devices formed on the crystalline silicon if the fault moves to a surface of the silicon.
After formation of the semiconductive ingot, the ingot is cut into thin wafers. The wafers are then subjected to further processing to form integrated circuitry on them.
The processing to form integrated circuitry on the silicon wafer generally involves various heating and cooling steps. Such steps cause the wafer to radially expand and contract. The degree of expansion and contraction are frequently not equal at the center of the wafer relative to regions of the wafer more adjacent a radially outer periphery of the wafer. Such unequal or uneven expansion of regions of the wafer can result in sheer stress between vertically stacked planes of the crystalline lattice. As sheer stress can lead to adjacent planes in the crystalline lattice slipping or sliding relative to one another, the sheer stress can upset the monocrystalline lattice of the silicon wafer. Such slippage of the planes in the crystalline lattice is referred to herein as "slip generation". Upsets in the lattice of the wafer can generate defects which adversely affect integrated circuits subsequently formed on the wafer.
A continuing trend in semiconductor wafer processing is to utilize larger and larger diameter wafers. Problems associated with lattice slipping are expected to become more pronounced as wafers become ever larger.
It would be desirable to develop methods for avoiding generation of lattice slippage in wafers, and to develop monocrystalline semiconductive material wafers and ingots treated to alleviate slippage within the crystalline lattices of the wafers and ingots.